In computer systems, a gap between central processing unit (CPU) speed and memory latency makes processor performance dependent on management of memory subsystems, particularly when multiple threads can execute simultaneously in a system, (e.g., simultaneous multithreading system (SMT), chip level multithreading system (CMP)). These systems mandate decisions about providing private cache resources (e.g., static partitions) to each thread or allowing threads to share a cache. However, private caches are prone to internal fragmentation and thus cache sharing is an alternative that commonly provides better performance.
In a shared cache, lines from one thread may be evicted by a fill initiated by a different thread. If the replaced cache line was not intended to be replaced by the first thread before its next reuse, this thread will suffer a cache miss for an access that would have been a cache hit if the thread was executing alone. Depending on the frequency of this type of event the system may suffer from suboptimal performance. Additionally, fairness between threads could be affected, resulting in thread starvation, priority inversion, and so on. These issues may continue while operating system (OS) and platform architectures schedule threads irrespective of thread sharing behavior and thread affinity.